Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA |
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Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc |
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Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups |
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Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures |
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Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies |
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500+ Engineers have been trained across the globe |
Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts |
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Executed Full Chip, Sub-System and block levels creating partitions |
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Have worked on Signoff like STA, PV, IR etc. |
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Experienced with 6 years in training who has held various levels of trainings |
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Trained about 650+ engineers |
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Trainer brings in experience from multiple MNCs with about 16+ years of industry experience |
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Trainer is leading a team of 60+ engineers currently |
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Working on Full Chip and methodology development |
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Technology node expertise from 7nm till 250nm across various foundries |
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Strong hands on experience in Synopsys and Cadence tool sets |
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Strong in TCL and PERL |
