Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is the goal of Physical Design.
15+ week program |
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Program covers all aspects of Netlist2GDS flow |
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Every topic and sub-topics are discussed in detail with practical aspects and hands-on sessions |
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Covers advanced concepts in Digital Design, CMOS, PnR flow, Signoff STA, Physical Verification, Low Power methodologies, Logic Equivalence Check and TCL scripting |
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Our designs are co-developed with inputs from industry experts |
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Soft Skill training |
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Resume preparation support |
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Regular assessment test to identify the areas that candidate needs to improve |
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Enable learning through regular theory and Labs assignments |
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Course completion Certificate after successful completion of the program |
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The path to industry would be very clear once this program is successfully completed |
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Labs can be accessed through VPN (24x7) from anywhere |
Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA |
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Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc |
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Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups |
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Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures |
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Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies |
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500+ Engineers have been trained across the globe |
Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts |
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Executed Full Chip, Sub-System and block levels creating partitions |
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Have worked on Signoff like STA, PV, IR etc. |
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Experienced with 6 years in training who has held various levels of trainings |
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Trained about 650+ engineers |
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Trainer brings in experience from multiple MNCs with about 16+ years of industry experience |
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Trainer is leading a team of 60+ engineers currently |
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Working on Full Chip and methodology development |
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Technology node expertise from 7nm till 250nm across various foundries |
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Strong hands on experience in Synopsys and Cadence tool sets |
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Strong in TCL and PERL |
TCL (Tool Command Language) is the basis of every EDA tool shell. Understanding of how to handle the objects like cell, net, pin, port etc and virtual objects like clock, timing values etc becomes very important for any part of ASIC flow. TCL expertise would help the candidate in faster scripting and design closure.
Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA |
|
Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc |
|
Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups |
|
Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures |
|
Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies |
|
500+ Engineers have been trained across the globe |
Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts |
|
Executed Full Chip, Sub-System and block levels creating partitions |
|
Have worked on Signoff like STA, PV, IR etc. |
|
Experienced with 6 years in training who has held various levels of trainings |
|
Trained about 650+ engineers |
|
Trainer brings in experience from multiple MNCs with about 16+ years of industry experience |
|
Trainer is leading a team of 60+ engineers currently |
|
Working on Full Chip and methodology development |
|
Technology node expertise from 7nm till 250nm across various foundries |
|
Strong hands on experience in Synopsys and Cadence tool sets |
|
Strong in TCL and PERL |
Timing is the heartbeat of the chip. Every action performed inside the chip is driven by the clock pulse and the synchronous circuits work in tandem to give desired output at a desired speed. STA is one of the most important aspects of any design closure.
Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA |
|
Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc |
|
Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups |
|
Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures |
|
Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies |
|
500+ Engineers have been trained across the globe |
Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts |
|
Executed Full Chip, Sub-System and block levels creating partitions |
|
Have worked on Signoff like STA, PV, IR etc. |
|
Experienced with 6 years in training who has held various levels of trainings |
|
Trained about 650+ engineers |
|
Trainer brings in experience from multiple MNCs with about 16+ years of industry experience |
|
Trainer is leading a team of 60+ engineers currently |
|
Working on Full Chip and methodology development |
|
Technology node expertise from 7nm till 250nm across various foundries |
|
Strong hands on experience in Synopsys and Cadence tool sets |
|
Strong in TCL and PERL |
Engineers who want to get deeper knowledge on Timing analysis |
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Engineers who want to extend to STA from other streams like PD and Synthesis |
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Engineers who want to improve their scripting skills w.r.t. timing signoff |
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Engineers who want to understand ECO cycles for final design closure |
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Engineers who have completed PD training and want to get more deep into STA closure |
