Physical Design - Integrated (PD)

Why PD?

Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is the goal of Physical Design.

Course overview - PD

20 weeks program

Program covers all aspects of RTL to GDSII flow (refer syllabus for integrated)

Every topic and sub-topic covers industry oriented practical aspects

Every topic and sub-topic is taught with hands-on lab from RTL to GDSII

In depth coverage of topics like Advanced Digital Design, CMOS, PnR flow, Pre-Layout STA and Sign-Off STA, Physical Verification, Low Power Methodologies, Logic Equivalence Check and TCL Scripting are key differentiators in the program

Curriculum and projects are co-developed with inputs from Industry experts

Soft skill training on the fly during the sessions

Resume preparation guidance

Regular assessment of areas where program members need improvement

Thorough in depth learning by interlinked theory and labs in parallel

Course completion certificate after completion of program

Trainers and Mentors available anytime for discussion

Path to VLSI industry will be clear once this program is completed

Labs can be accessed 24x7 through VPN from anywhere



Trainer 1 - PD

Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA

Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc

Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups

Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures

Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies

500+ Engineers have been trained across the globe

Trainer 1
ABOUT US

Trainer 2 - PD

Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts

Executed Full Chip, Sub-System and block levels creating partitions

Have worked on Signoff like STA, PV, IR etc.

Experienced with 6 years in training who has held various levels of trainings

Trained about 650+ engineers

Trainer brings in experience from multiple MNCs with about 16+ years of industry experience

Trainer is leading a team of 60+ engineers currently

Working on Full Chip and methodology development

Technology node expertise from 7nm till 250nm across various foundries

Strong hands on experience in Synopsys and Cadence tool sets

Strong in TCL and PERL

Syllabus - PD

  •   Module 1: Advanced Digital Design
  •   Module 2: Introduction to Layout & CMOS
  •   Module 3: Introduction to Linux Operating System
  •   Module 4: Introduction to SOC Design flow
  •   Module 5: RTL Synthesis & Pre-Layout STA
  •   Module 6: Introduction to DFT
  •   Module 7: Introduction to Physical Design Flow
  •   Module 8: Design Planning (Floorplan)
  •   Module 9: Power-Routing & Introduction to IR-Drop Analysis
  •   Module 10: Static Timing Analysis
  •   Module 11: Pre-Placement & Std-Cell Placement
  •   Module 12: Scan-Chain Re-Ordering and Re-partitioning
  •   Module 13: Timing Optimization
  •   Module 14: CTS & Post-CTS Timing Optimization
  •   Module 15: Routing
  •   Module 16: Physical Verification
  •   Module 17: RC Extraction using industry RC extraction tool
  •   Module 18: Sign-off STA Checks with STA tool
  •   Module 19: Timing Closure & ECO Implementation.
  •   Module 20: Introduction to Equivalence Check
  •   Module 21: IR-Drop and EM Analysis Flow
  •   Module 22: Introduction to Low Power & UPF
  •   Module 23: TCL Scripting for creating procs for designs
  •   Module 24: Introduction to Advanced STA Topics
  •   Module 25: Introduction to Fin-FET & DPT.
  •   Module 26: Introduction to 7nm & Floorplan Challenges.
  •   Module 27: Final Projects

Labs - PD

  •  Complex block level implementation
  •  Multiple designs covering full PnR end to end

EDA Tools and Projects - PD

    .
  •  Most prominent and widely used tools in the industry
  •  Multiple Projects including CPU Cores

Who can attend - PD

  •  Engineering Graduates (BTech, BE, BS)
  •  Engineering Post-Graduates (MTech, ME, MS)
  •  Experienced Engineers who want to change their domain to Physical Design
  •  Experienced Engineers who want to improve their Physical Design skills
  •  College faculties who want to gain Industry knowledge
onlyfans leakedonly fan leaks