Physical Design interview questions - Part 11

Physical Design interview questions - Part 11

  1. Is NDR better or shielding better for clock tree synthesis?
  2. Design a circuit which outputs a frequency of 2f with an input of f.
  3. A, B, C are unsigned 32-bit numbers. How many bits are needed for Y = (A * B) +C?
  4. Design a Synchronous 2-bit counter using 2 DFFs?
  5. Write verilog code for a Flip-flop with an asynchronous reset
  6. How do you declare arrays in perl? Declare an array {3, 2}.
  7. What are feedthough paths?
  8. What is noise margin?
  9. Why should we use inverters on the clock tree to minimize clock cycle distortion?
  10. Write UPF code for a small design.
  11. What techniques will you use to mitigate channel congestion?
  12. What are the advantages and disadvantages of different placement algorithms?
  13. After base tapeout how do you implement metal only ECOs?
  14. Design a sequence detector of the pattern 11011.
  15. Design an XOR gate using only two 2:1 mux.
  16. Design a FSM for traffic light controller
  17. Design a johnson counter in verilog.
  18. Equations for resistance and capacitance of a wire.
  19. What happens if we increase the number of contacts or via between metal layers (redundant via insertion)?
  20. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A &B, which one would you place near the output?
  21. Explain the operation of a 6-T SRAM cells.
  22. What is body effect?
  23. What is latch up? Explain the methods used to prevent it?
  24. What is resistive shielding?
  25. Details on FD-SOI technology?
  26. What are various synthesis optimization techniques?
  27. What is retiming? How is it used to optimize the design?
  28. How are standard cells characterized? Example of characterization of a AND gate
  29. Given a library with several functions, channel lengths, VT-types, how do you prune the cells list for synthesizing the design?
  30. In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why?
  31. The blocks are timing clean and when integrated at top-level there are lot of setup and hold violations. What are all the possible causes of these new violations?
  32. What is binning? How do you determine the criterion for CPU binning?
  33. What is DVFS?
  34. How do you resolve congestion?
  35. Explain in detail how clock tree is built by the tool?
  36. Explain the tool process flow of standard cell placement?
  37. Explain skew, latency, insertion delay?
  38. What will be your road map for PnR flow if starting utilisation is 80% and it’s a rectilinear block?
  39. In how many corners did you close the timing? Write the corner names. Among these which was the hardest corner to close and why?
  40. Why assign statements are not allowed   in netlist? What will happen if we proceed with it?
  41. Halo is used to protect pins of macro why? Why only for macro?
  42. Why vss is preferred over vdd for shielding?
  43. Whether end cap cells will be used for power continuity? If yes why?
  44. Why spacing between abutted macros is given?  Why that spacing is required in fabrication?
  45. Whether min pulse width violation effect timing or functionality of design? How?
  46. Whether any factor other than temperature depend on net delay?
  47. How you go about fixing timing violations for latch- latch paths?
  48. How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
  49. What are various formal verification issues you faced and how did you resolve?

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